Field of the Invention
Embodiments of the invention relate to a display device and a method for driving the same.
Discussion of the Related Art
A flat panel display may be implemented as a liquid crystal display (LCD), an organic light emitting display, an electrophoresis display (EPD), and a plasma display panel (PDP).
An active matrix display device includes a thin film transistor (TFT) serving as a switching element in each pixel. A driving circuit of the display device applies an input image to the pixels. The driving circuit of the display device includes a data driving circuit outputting a data voltage, a gate driving circuit (or a scan driving circuit) outputting a gate pulse (or a scan pulse) synchronized with the data voltage, and a timing controller for controlling operation timings of the data driving circuit and the gate driving circuit. The data driving circuit may include a plurality of source driver integrated circuits (ICs). The gate driving circuit may include a plurality of gate driver ICs.
The timing controller supplies digital video data, clocks for sampling the digital video data, a control signal for controlling operations of the source driver ICs, etc. to the source driver ICs through a standard interface, for example, a mini low voltage differential signaling (LVDS) interface. The source driver ICs convert the digital video data received from the timing controller into an analog data voltage and supply the analog data voltage to data lines.
When the timing controller is connected to the source driver ICs in a multidrop manner through the mini LVDS interface, red (R) data transmission lines, green (G) data transmission lines, blue (B) data transmission lines, control lines for controlling operation timings of an output and a polarity conversion operation of the source driver ICs, clock transmission lines, etc. may be implemented between the timing controller and the source driver ICs. In the mini LVDS interface, RGB data, for example, RGB digital video data and a clock are transmitted via differential signal pair. In one example, when odd data and even data are simultaneously transmitted, at least 14 lines for the transmission of the RGB data are implemented between the timing controller and the source driver ICs. When the RGB data have 10 bits, 18 lines are implemented. Thus, multiple lines may be formed on a source printed circuit board (PCB) mounted between the timing controller and the source driver ICs. Hence, the source PCB is implemented with a large surface area to accommodate widths of the multiple lines.
A new signal transmission protocol (hereinafter referred to as “an EPI (clock embedded point-to-point) interface protocol”), which connects the timing controller with the source driver ICs in a point-to-point manner to minimize the number of lines between the timing controller and the source driver ICs and to stabilize the signal transmission, was disclosed in U.S. Pat. Nos. 7,898,518, 7,948,465, and 8,330,699 corresponding to the present applicant, and which are hereby incorporated by reference in their entirety.
The EPI interface protocol has the following characteristics (1) to (3).
(1) A transmitting terminal of the timing controller is connected with receiving terminals of the source driver ICs via signal line pairs (hereinafter referred to as “EPI line pairs”) without the line sharing in the point-to-point manner.
(2) Separate clock line pairs are not connected between the timing controller and the source driver ICs. The timing controller transmits a clock signal and digital data to the source driver ICs through the EPI line pairs. The digital data includes video data of an input image and control data for controlling the operations of the source driver ICs.
(3) A clock recovery circuit for clock and data recovery (CDR) is embedded in each of the source driver ICs. The timing controller transmits a clock training pattern signal, namely, a preamble signal to the source driver ICs, so that an output phase and an output frequency of the clock recovery circuit may be locked. The clock recovery circuit embedded in each source driver IC generates an internal clock in response to the preamble signal input through the EPI line pairs and locks a phase and a frequency of the internal clock.
When the phase and the frequency of the internal clock are locked, the source driver ICs indicate, with a lock signal, an output stabilization state to the timing controller. For example, the source driver IC generates a lock signal with a high logic level to indicate the output stabilization state to the timing controller.
As described above, in the EPI interface protocol, the timing controller transmits the preamble signal to the source driver ICs before transmitting the control data and the video data of the input image to the source driver ICs. The clock recovery circuit of the source driver IC performs a clock training operation in response to the preamble signal and stably locks the phase and the frequency of the internal clock. When the phase and the frequency of the internal clock are stably locked, a data link, to which the video data of the input image is transmitted, is formed between the source driver ICs and the timing controller. After the lock signal is received from the last source driver IC, the timing controller starts to transmit the video data and the control data to the source driver ICs.
When the output phase and the output frequency of the clock recovery circuit embedded in any one of the source driver ICs are unlocked, the source driver ICs indicate, with the lock signal, the output phase and the output frequency are unlocked. For example, the lock signal may be inverted to a low logic level. The last source driver IC transmits the lock signal of the low logic level to the timing controller. When the lock signal is inverted to the low logic level, the timing controller transmits the preamble signal to the source driver ICs and resumes the clock training operations of the source driver ICs.
In the display device, touch sensors may be embedded in a pixel array in an in-cell type, so as to implement a touch user interface (UI). When the touch sensors are embedded in the pixel array of the display device, a pixel driving period and a touch sensor driving period are time-divided so as to prevent interference between the touch sensors and pixels of the pixel array, because the touch sensors and the pixels are coupled through a parasitic capacitance. When a voltage of the pixel changes in the touch sensor driving period, the changed voltage of the pixel is applied to the touch sensor through the parasitic capacitance and thus generates a noise in an output of the touch sensor. However, the EPI interface protocol does not address a control method capable of preventing changes in the voltage of the pixel in the touch sensor driving period when the pixel driving period and the touch sensor driving period are time-divided.